The present invention relates to an integrated circuit, such as a semiconductor memory device, and more particularly, an integrated circuit for reducing the number of additional circuits required when the integrated circuit is tested.
In a system having a plurality of integrated circuits, an integrated circuit, such as a semiconductor memory device, is used for data storage. When a data processor device (for example, a central processor unit CPU) demands data, the integrated circuit outputs the demanded data in accordance with an address inputted from the data processor device or stores the demanded data at a cell memory in accordance with the address.
As the operating speed of a system having integrated circuits increases, and a technique related to an integrated circuit develops, the integrated circuit is required to output and store data more rapidly. Recently, integrated circuits have been required to store more data and to perform READ/WRITE operations more rapidly.
As described above, design, fabrication, and testing of integrated circuits is becoming more complicated and difficult.
FIG. 1 is a block diagram describing a circuit related to a test operation of a conventional semiconductor memory device.
Referring to FIG. 1, the semiconductor memory device includes a command and address block 120, a test mode decoder 140, a plurality of latches 160_1 to 160_6 and a plurality of test control circuits 180_1 to 180_6. The plurality of test control circuits 180_1 to 180_6 are for controlling various test operations performed in elements of an internal semiconductor memory device.
The elements may be divided for testing into a number of groups according to different criteria, including, for example, into a peripheral region and a core region according to a layout, into a bank, an input/output peripheral circuit and an internal voltage circuit according to a function, or into parts related to a read/write operation region and a precharge operation region according to an internal performing operation.
Many kinds of test modes are required to sort various inferior parts in the semiconductor memory device. The many kinds of test modes are identified by combining a command CMD and an address ADD inputted to the command and address block 120.
The command and address block 120 generates a test mode code TMCODE for representing a test mode selected among various test modes, a test mode start signal TM_SET for representing a start of the test mode according to the test mode code TMCODE, and the test mode reset signal TM_RESET for representing a reset of the test mode according to the test mode code TMCODE by decoding the command CMD and the address ADD.
The test mode decoder 140 receives the test mode code TMCODE and the test mode start signal TM_SET and activates a test mode signal TM_A to TM_F for testing the element according to the decoded command CMD and the address ADD received. The test mode signals TM_A to TM_F are latched in the plurality of latches 160_1 to 160_6 corresponding to the test mode reset signal TM_RESET and used for various tests by the plurality of test control circuits 180_1 to 180_6 in the internal semiconductor memory device.
The test mode signals TM_A to TM_F are transmitted to the plurality of test control circuits 180_1 to 180_6 to change a test mode and a start timing of the test operation. The test mode signal TM_A to TM_F is stored in the plurality of latches 160_1 to 160_6 so as to perform a plurality of test modes simultaneously. The plurality of latches 160_1 to 160_6 are reset respectively when the test mode reset signal TM_RESET is inputted from the command and address block 120. The test mode reset signal TM_RESET can be generated by a result of decoding the command CMD and the address ADD or a command of a mode resistor set MRS.
As described above, for transmitting the test mode signal TM_A to TM_F to the plurality of test control circuit 180_1 to 180_6, a plurality of test mode signal transmission line TM_A′ to TM_F′ is required.
If a distance from the plurality of latches 160_1 to 160_6 to the plurality of test control circuit 180_1 to 180_6 is greater, a length of the test mode signal transmission line TM_A′ to TM_F′ has to lengthen like a global input/output (I/O) lines GIO.
To store much more data, to input/output data more rapidly and to reduce a power consumption, an internal structure of the semiconductor memory device has become more complicated. Therefore, test modes for the semiconductor memory device have increased and test items of the semiconductor memory are varied. There are various test methods to test for high conductivity of a semiconductor memory device. As the test mode is changed in accordance with an operating environment and its surrounding environment, a number of the test mode signal TM_A to TM_F are increased, and a number of the test mode signal transmission line TM_A′ to TM_F′ is also increased consequently.
FIG. 2 illustrates a structure for data transmitting between the peripheral region and the core region of a conventional semiconductor memory device.
Referring to FIG. 2, the semiconductor memory device comprises the core region including a unit cell for storing data, the peripheral region transmitting data to the core region or external and the global I/O lines GIO connecting the peripheral region to the core region.
Concretely, the respective global I/O lines GIO transmit data between a I/O sense amplifier IOSA and a test mode driver TM_DRV of the core region and the I/O multiplexer DQ_MUX and a pad sense amplifier DIN_IOSA of the peripheral region.
When a read operation is performed, data from a unit cell is transmitted to an I/O multiplexer DQ_MUX through the I/O sense amplifier IOSA, and outputted to an external. When a write operation is performed, data inputted externally are detected by the pad sense amplifier DIN_IOSA, and transmitted to a write driver WT_DRV and stored at the unit cell.
As the operating speed of the semiconductor memory device increases and the number of processing (for example, reading or writing) data bits at one-time are increased, the number of the global I/O lines GIO is increased. For example, when 16 bit data is inputted or outputted at one time, 32 of the global I/O lines GIO are required for double data rate (DDR). 64 of the global I/O lines GIO are required for DDR2, and 128 of the global I/O lines GIO are required for DDR3.
FIG. 3 is a circuit diagram describing an internal structure of the semiconductor memory device depicted in FIG. 2. Referring to FIG. 3, the I/O sense amplifier IOSA, the I/O multiplexer DQ_MUX and the pad sense amplifier DIN_IOSA are each connected to the global I/O lines GIO and transmit data, when a read operation or a write operation is performed. When the read operation or the write operation is not performed, they are isolated to the global I/O lines GIO.
In detail, the I/O sense amplifier IOSA and the pad sense amplifier DIN_IOSA include driving units which include a PMOS transistor and a NMOS transistor. When the read operation is performed, the PMOS and NMOS transistors in the I/O sense amplifier IOSA are turned-on in response to signals RD_H_B and RD_L corresponding data outputted from the unit cell, and supply a drive voltage or a ground voltage for the global I/O lines GIO. When the read operation is not performed, the PMOS and NMOS transistors in the I/O sense amplifier IOSA are turned-off, so that the I/O sense amplifier IOSA is in a floating state by disconnecting to the global I/O lines GIO.
Similar to the I/O sense amplifier IOSA, the pad sense amplifier DIN_IOSA includes driving units which include a PMOS transistor and a NMOS transistor. The PMOS and NMOS transistors turned-on in response to signals WT_H_B and WT_L correspond to an input data from the external, and supply a drive voltage or a ground voltage for the global I/O lines GIO, when the write operation is performed. When the write operation is not performed, the PMOS and NMOS transistors are turned-off, so that the I/O sense amplifier IOSA is in a floating state by disconnecting to the global I/O lines GIO.
The write driver WT_DRV and the I/O multiplexer DQ_MUX includes a transmission gate, not driving unit which includes a PMOS transistor and a NMOS transistor. The global I/O lines GIO are connected to the I/O multiplexer DQ MUX in response to read enable signal RD_EN_B and RD_EN, when the read operation is performed. The global I/O lines GIO are connected to the write driver WT_DRV in response to write enable signal WT_EN_B and WT_EN, when write operation is performed. On the contrary, when the read/write operation is not performed, the connection of the write driver WT_DRV/the I/O multiplexer DQ_MUX and the global I/O lines GIO is disconnected and the global I/O lines GIO are in a floating state.
Recently, as the number of the global I/O lines GIO has increased, a region where the global I/O lines GIO is located has begun to affect the whole semiconductor chip. Particularly, as the transmission line for transmitting test data as well as the global I/O lines GIO are increased, a region where the global I/O lines GIO and the transmission line are located is further increased. This increased region becomes a burden to a high integrated circuit of semiconductor memory device.